As the Internet rapidly develops, a future Ethernet interface bandwidth may have two rates: 400GE (gigabit Ethernet, gigabit Ethernet) and 1TE (terabit Ethernet).
In the IEEE 802.3ba standard, a 40GE/100GE Ethernet PCS (Physical Coding Sublayer, physical coding sublayer) uses an implementation method of self-synchronizing scramble and descramble (Self Synchronizing Scramble and Descramble) at an aggregate level before multi-lane distribution. Synchronizing scramble and descramble may be self-synchronizing scramble/descramble on aggregate level (Self Synchronizing Scramble and Descramble on Aggregate Level, Scramble on AL). Referenced may be made to block distribution (block distribution) in the IEEE 802.3ba for the multi-lane distribution. In the existing 100GE standard, self-synchronizing scramble (which may be executed by a logic circuit for implementing self-synchronizing scramble) and self-synchronizing descramble (which may be executed by a logic circuit for implementing self-synchronizing descramble) occur before the multi-lane distribution, and therefore they are also referred to as the Scramble on AL.
A self-synchronizing scrambling method cannot perform effective pipelined processing because of a feedback characteristic of the method. In the 100GE standard, a high-performance parallel processing Scramble on AL solution requires that: when a working frequency is 312.5 MHz, 40 bytes of data can be processed at a time, and about 0.4 k LUT (Look Up Table, look up table) resources are needed. The LUT is one of main logic units in an FPGA (Field Programmable Gate Array, field programmable gate array) chip. Further, if a future 400GE standard is still implemented according to the high-performance parallel processing Scramble on AL solution, it is required that under a working frequency of 312.5 MHz, 160 bytes of data can be processed at a time, and about 10.8 k LUT resources are needed. From 100GE to 400GE, a bandwidth becomes four times the original, and occupied LUT resources are 20-30 times the original.
With appearance of concepts such as a Flexible Grid (flexible grid), a Flexible OTN (Flexible Optical Transmission Network, flexible optical transmission network), and a Flexible Bandwidth optical network (flexible bandwidth optical network), a related concept such as a flexible Ethernet characterized by that Ethernet interfaces are channelized and may be flexibly grouped also appears correspondingly. For example, lane resources, which originally belong to a fixed 400GE Ethernet interface completely, flexibly bear, in a sharing manner of flexible configuration and flexible grouping, flexible Ethernet interfaces which are grouped in various manners such as one 400GE Ethernet interface, one 300GE Ethernet interface+one 100GE Ethernet interface, two 200GE Ethernet interfaces, four 100GE Ethernet interfaces, eight 50GE Ethernet interfaces or sixteen 25GE Ethernet interfaces. During an implementation process of the flexible Ethernet, a MAC data stream processed by a MAC (Media Access Control, media access control) sublayer is decomposed into multiple sub MAC streams after a sub MAC stream distribution process, and each sub MAC stream separately performs self-synchronizing scramble and multi-lane distribution processing. In the IEEE 802.3ba 100GE standard, in implementation of a flexible Ethernet with a high interface bandwidth such as 400 Gbps or 1 Tbps, if the Scramble on AL solution similar to that in the 100GE standard is used, after sub MAC streams are distributed and before the sub MAC streams are distributed to multiple PCS lanes (PCS lanes), it is necessary to separately complete scramble processing of the various flexibly configured sub MAC streams, that is, Scramble on AL of Sub MAC Stream (self-synchronizing scramble on aggregate level of sub MAC stream).
As an Ethernet interface bandwidth rate is improved rapidly, in the Scramble on AL solution and the Scramble on AL of Sub MAC Stream solution, a data bandwidth processed by a logic circuit for implementing scramble and descramble increases, which results in a geometric growth in an aspect such as occupied logical resources. As a result, chip design requirements are improved. That is, costs in various aspects such as a chip area, power consumption, and timing convergence are correspondingly and significantly increased. Therefore, it is not conducive to implementation of an FPGA (Field Programmable Gate Array, field programmable gate array) or an ASIC (Application Specific Integrated Circuit, application specific integrated circuit) of a system.